Deep link: ?example=esp32-match · tool stays general for every other example
The problem in one sentence
Many ESP32 bare-chip designs do not present 50 Ω at the RF pin.
Espressif’s hardware design guidelines list the RF output impedance in the neighborhood of
\(30 + j10\,\Omega\) (or \(35 + j10\,\Omega\) on some packages).
A π-type CLC matching network (shunt C · series L · shunt C) is the usual bridge
toward a 50 Ω antenna feed, U.FL, or microstrip — for the 2.4 GHz band used by
Wi‑Fi and Bluetooth.
Not a drop-in gerber recipe.
Values below are illustrative lumped starting points. Real boards need a VNA (or at least careful
copy of a proven reference layout): package parasitics, DC block, vias, ground plane, plastic, and
the PCB inverted‑F antenna (IFA) all move the match.
What impedance are we matching?
Two different things get mixed up in forum threads:
Chip RF pin — Espressif’s stated \(Z_{\mathrm{chip}}\) (e.g. \(30+j10\,\Omega\)).
That is what this lesson treats as the load \(Z_L\) in the Smith tool.
Antenna / IFA — ideally near 50 Ω at the feed after geometry is right, but
on a real board it often is not. Then you match chip → measured antenna, not chip → ideal 50 Ω.
Module users (ESP32‑WROOM, etc.) usually already have a match on the module to a 50 Ω pad —
their problem is “pad → antenna,” which is a different story. This part is about
bare chip → 50 Ω system.
Package variants (typical published ballparks)
Part / package (examples)
RF pin Z (approx.)
ESP32 QFN 6×6
30 + j10 Ω
ESP32 QFN 5×5
35 + j10 Ω
ESP32‑C3 / S2 / S3 family (check your HG)
Same neighborhood — always read your hardware design guidelines
In the Smith tool, try changing the load from \(30+j10\) to \(35+j10\) and hit
Auto-tune or nudge the CLC values — you will see the match move.
Why a CLC π network?
Espressif recommends a π-type CLC structure for the matching network:
two shunt capacitors and a series inductor between the RF pin and the antenna side.
Beyond transforming impedance, that arrangement also helps with harmonic filtering compared to a bare L-section.
About the numbers on the schematic.
The part values below are not copied from Espressif’s BOM or from a Stack Exchange answer.
They are an ideal lumped fit we solved so that
\(Z_L = 30 + j10\,\Omega\) looks like \(50\,\Omega\) at \(2.45\,\mathrm{GHz}\)
(deep return loss on the math model). Espressif’s hardware design guidelines give the
topology (CLC π) and the pin impedance ballpark; real boards use nearby
E‑series values and then tune with a VNA because layout parasitics dominate at 2.4 GHz.
Treat 1.65 pF / 2.65 nH / 2.33 pF as a teaching starting point, not a guaranteed PCB recipe.
CLC π as drawn in the matcher: Z₀ (50 Ω system) on the left,
series L on the bus, shunt Cs to ground,
Z_load = ESP32 RF pin on the right.
Values are the lab’s ideal-model starting point @ 2.45 GHz (see note above).
On the Smith chart, each shunt C is a move on a constant‑G arc; the series L is a move
on a constant‑R arc. Three strokes is enough to land near the chart center at one design frequency
(here 2.45 GHz), with usable return loss across the ~2.40–2.50 GHz ISM band.
You do not need a multi‑GHz match for a 2.4 GHz radio.
The useful window is the ISM band used by Wi‑Fi (2.4) and Bluetooth — roughly
2.40–2.50 GHz, with design frequency near mid-band 2.45 GHz.
The lab preset sweeps exactly that range so the S11 plot is honest about “good enough across the channel,” not a deep notch at one frequency with junk everywhere else.
How to use the live lab
Open the preloaded tool (button above or at the bottom). You should see load
\(R=30\), \(X=10\), design F 2.45 GHz, band 2.40–2.50 GHz, and a three-element CLC chain.
Note return loss at design F and the green match-bandwidth readout (e.g. RL ≥ 15 dB).
Toggle Matched S11 vs Raw S11 — raw is the chip alone into 50 Ω (poor); matched is with the CLC.
Change load to \(35+j10\) (QFN 5×5 style). Watch the match detune; Auto-tune or drag endpoints to recover.
Hit Build to snap to stock E-series values — a real BOM rarely keeps three perfect ideal numbers.
Layout note (from Espressif-style practice):
keep the CLC as close as possible to the RF pin; short RF traces; solid RF ground under the match;
follow keep-outs around the IFA. Component values without layout discipline are wishful thinking.
FAQ
Is 30+j10 exact for my ESP32?
No — it is a published ballpark for certain packages. Check the hardware design guidelines for
your silicon/package revision.
Can I connect an antenna straight to the pin?
On bare-chip designs, skipping the match usually costs serious range (high VSWR into a 50 Ω antenna).
Modules already include a match to the module RF pad.
What about an inverted‑F that is not 50 Ω?
Measure or EM-simulate the antenna feed, then match \(Z_{\mathrm{chip}}\) toward that load
(or redesign the IFA). The Smith tool accepts fixed \(R+jX\), Z(f) tables, or S-parameters.
Ready: open the interactive ESP32 match (preloaded CLC π @ 2.45 GHz).