Common-source · Load Line & Q-point — Voltage Regulation

Along the way

1
The resistor draws a line, not a curve. Source at 0 V. Stack is \(V_{\mathrm{DD}}\rightarrow R_D\rightarrow\) drain — that is the schematic. Intercepts: \((V_{\mathrm{DD}},0)\) and \((0,V_{\mathrm{DD}}/R_D)\). The FET must sit on that rose line and on one family member.
2
Wiggle the gate, stay on the same line. New \(V_{\mathrm{GS}}\) → a different family curve → Q slides along the load line. \(\Delta I_D\) becomes \(\Delta V_{\mathrm{DS}}=-R_D\,\Delta I_D\). That swing is \(v_{\mathrm{out}}\).
3
Live on the flat part. Saturation: \(I_D\) set by \(V_{\mathrm{GS}}\), almost independent of \(V_{\mathrm{DS}}\). MOSFET “linear / triode” is a different word — that is the switch-ON corner, not amp bias.
4
The \(I_D\)–\(V_{\mathrm{GS}}\) plot is allowed to be curved. Square-law is the device. A small wiggle uses the local slope \(g_m=k(V_{\mathrm{GS}}-V_{\mathrm{th}})\). \(|A_v|\approx g_m R_D\) only while Q stays in saturation.
5
Fall into triode and the amp dies. Too much \(V_{\mathrm{GS}}\) or too large \(R_D\) pulls Q left of \(V_{\mathrm{DS,sat}}\). The FET looks like a resistor; the \(g_m R_D\) number is not the gain.
6
Cutoff is the other rail. Gate below threshold → \(I_D\approx0\) → \(V_{\mathrm{out}}\approx V_{\mathrm{DD}}\). Not a bias point for a linear common-source stage.

Source stays at 0 V. The rose line is the resistor, not another MOSFET curve. \(|A_v|\) is quoted only in saturation. \(k\) here is in mA/V² — a small FET, not a power switch.

Lab · Load line meets the family

Source at 0 V · gold Q is the only DC solution both the FET and \(R_D\) accept

Saturation —

\(V_{\mathrm{GS}}\) (V) \(V_{\mathrm{DD}}\) (V) \(R_D\) (kΩ) \(V_{\mathrm{th}}\) (V) \(k\) (mA/V²)

Circuit · \(V_{\mathrm{DD}}\rightarrow R_D\rightarrow\) drain · gold node is \(V_{\mathrm{out}}\) · rail shows amp vs triode

Matches the knobs. Open, Run, probe V(Vin) and V(Vout).

\(I_D\) vs \(V_{\mathrm{DS}}\) · family · rose = load line · gold = Q

\(V_{\mathrm{out}}\) vs \(V_{\mathrm{GS}}\) · what the circuit delivers

\(I_D\) vs \(V_{\mathrm{GS}}\) · parabola · tangent is \(g_m\)

\(V_{\mathrm{out}}=V_{\mathrm{DS}}\)—

\(I_D\)—

\(V_{\mathrm{ov}}\)—

\(V_{\mathrm{DS,sat}}\)—

\(g_m\)—

\(|A_v|\approx g_m R_D\)—

\[ V_{\mathrm{out}} = V_{\mathrm{DD}} - I_D R_D \]

→ —

\[ I_{D,\mathrm{sat}} = \tfrac12 k\,(V_{\mathrm{GS}}-V_{\mathrm{th}})^2 \]

→ —

\[ g_m = k\,V_{\mathrm{ov}},\quad |A_v|\approx g_m R_D \quad(\mathrm{sat}) \]

→ —

\(k\) is lumped strength in mA/V². The gain number applies only in saturation. Saturation is drawn perfectly flat. Real parts slope a little, and a real load is often not a plain resistor.

Try it: (1) Textbook sat — gold Q mid-rail, finite \(|A_v|\), tangent on the parabola. (2) Cutoff — Q at the right end of the load line; \(V_{\mathrm{out}}\approx V_{\mathrm{DD}}\). (3) Triode clamp — Q left of \(V_{\mathrm{DS,sat}}\); gain greyed. (4) High gain — larger \(R_D\), still sat; \(|A_v|\) climbs. (5) Sweep \(V_{\mathrm{GS}}\) and watch Q slide on the same rose line.

Analog Intuition

Common-source · load line & Q-point

Lab · Load line meets the family