MOSFET Switching · Charging Cgs and Cgd — Voltage Regulation

Along the way

1
Three capacitors, one device. \(C_{\mathrm{GS}}\) gate-to-source, \(C_{\mathrm{GD}}\) gate-to-drain (Miller). \(C_{\mathrm{DS}}\) is drawn for orientation only — \(I_G\) never fills it (its voltage just follows \(V_{\mathrm{DS}}\)). This page is the two gate caps.
2
Turn-on is four scenes. Charge \(C_{\mathrm{GS}}\) to \(V_{\mathrm{th}}\) (delay) → \(I_D\) rises while \(V_{\mathrm{DS}}\) is still high → Miller: \(V_{\mathrm{GS}}\) sticks, \(C_{\mathrm{GD}}\) discharges, \(V_{\mathrm{DS}}\) falls to \(I_D R_{\mathrm{DS(on)}}\) — not zero — then finish charging the gate.
3
Miller is the long \(V\times I\) window. All of \(I_G\) goes into \(C_{\mathrm{GD}}\). Same shelf on the datasheet \(V_{\mathrm{GS}}\)–\(Q_g\) curve. Bigger \(C_{\mathrm{GD}}\) or \(V_{\mathrm{DD}}\) → more \(Q_{\mathrm{GD}}\) → more \(E_{\mathrm{sw}}\).
4
Current-limited \(I_G\) sets the clock, not the shape. \(I_G=(V_{\mathrm{DRV}}-V_{\mathrm{GS}})/(R_{\mathrm{drive}}+R_{\mathrm{g}})\). No separate current source. The Miller shelf on \(Q_g\) is still there even with a stiff driver — you just blast through it faster.
5
Optional \(R_{\mathrm{g}}\) (often 1–5 Ω) slows the edge. People add two to five ohms at the gate to kill ringing and overshoot. \(I_G\) drops, so \(t_r\) and \(t_f\) stretch and \(E_{\mathrm{sw}}\) goes up. Default here is 1 Ω. \(R_{\mathrm{drive}}\) stays in the driver.
6
Drive above the plateau or it never turns on. The shelf sits at \(V_{\mathrm{pl}}\approx V_{\mathrm{th}}+I_D/g_m\). If the gate rail is below that, \(V_{\mathrm{DS}}\) never falls. You stay in the high-\(V\times I\) region and cook the FET.
7
Energy this event, then \(\times f_{\mathrm{sw}}\). \(E_{\mathrm{sw}}\approx\tfrac12 V_{\mathrm{DD}}I_D(t_r+t_f)\). Average power is \(E_{\mathrm{sw}}f_{\mathrm{sw}}\). Frequency is a tax.
8
Not the full loss budget. No \(I^2R_{\mathrm{DS(on)}}\) bake-off, \(Q_{\mathrm{oss}}\), or \(Q_{\mathrm{rr}}\). Compare two FETs on the MOSFET Efficiency Tool. This page is the capacitance picture.

Cartoon hard-switch. \(I_G\) from the driver and the two resistors. Gold cursor is “now.”

Lab · Scrub a turn-on · watch which cap is charging

\(I_G=(V_{\mathrm{DRV}}-V_{\mathrm{GS}})/(R_{\mathrm{drive}}+R_{\mathrm{g}})\) · gold line is this instant

Delay —

\(V_{\mathrm{DD}}\) (V) \(I_D\) (A) \(C_{\mathrm{GS}}\) (nF) \(C_{\mathrm{GD}}\) (nF) \(f_{\mathrm{sw}}\) (kHz)

Through the event —

Device · which capacitor \(I_G\) is filling

\(R_{\mathrm{g}}\) Ω

Turn-on · \(V_{\mathrm{GS}}\), \(I_D\), \(V_{\mathrm{DS}}\) vs time

Datasheet · \(V_{\mathrm{GS}}\) vs \(Q_g\)

Scene—

\(Q_g\) so far—

\(Q_{\mathrm{GD}}\)—

\(t_r+t_f\)—

\(E_{\mathrm{sw}}\)—

\(P_{\mathrm{sw}}\)—

\(P_{\mathrm{gate}}\)—

\(V_{\mathrm{DS,on}}\)—

\[ t_f=Q_{\mathrm{GD}}/I_G \]

→ —

\[ E_{\mathrm{sw}}\approx\tfrac12 V_{\mathrm{DD}}I_D t_r+\tfrac12 I_D(V_{\mathrm{DD}}+V_{\mathrm{on}})t_f \]

→ —

\(I_G=(V_{\mathrm{DRV}}-V_{\mathrm{GS}})/(R_{\mathrm{drive}}+R_{\mathrm{g}})\). \(C_{\mathrm{GS}}\) charges exponentially; Miller is the one interval with constant \(I_G\) (stuck \(V_{\mathrm{GS}}\)). \(E_{\mathrm{sw}}\) is the \(V\times I\) overlap only. Gate-drive heat is \(Q_g V_{\mathrm{DRV}} f_{\mathrm{sw}}\), burned in the two resistors — \(R_{\mathrm{g}}\) does not change that energy, only the overlap. Cartoon constant caps, not \(C_{\mathrm{rss}}(V)\).

Try it: Same 0–30 nC frame on every FET. Low \(Q_g\) is a small die (higher \(R_{\mathrm{DS(on)}}\)). Low \(R\) is a wide die (more gate charge). 10 V class vs High-voltage moves \(V_{\mathrm{DD}}\) — watch the Miller shelf and \(V_{\mathrm{DS,on}}=I_D R_{\mathrm{DS(on)}}\). Raise \(R_{\mathrm{g}}\) to 5 Ω: \(I_G\) falls, time stretches, \(E_{\mathrm{sw}}\) climbs, \(Q_g\) does not.

Full converter loss stack: MOSFET Efficiency Tool.

Analog Intuition

MOSFET switching · charging \(C_{\mathrm{GS}}\) and \(C_{\mathrm{GD}}\)

Lab · Scrub a turn-on · watch which cap is charging