Synchronous Boost Timing & Current Ripple

Power · boost waveforms

Synchronous boost timing & current ripple

Key point: a CCM boost stores energy with the low-side FET on, then dumps it through the high-side sync FET. Duty is \(D=1-V_{\mathrm{in}}/V_{\mathrm{out}}\), not \(V_{\mathrm{out}}/V_{\mathrm{in}}\). Average inductor current is \(I_{\mathrm{out}}/(1-D)\), so a 12 V to 24 V converter already carries twice the load in \(L\).

Each step loads a preset. The chips in the lab are the same points.

1
Duty is the low-side on-time.
\(D=1-V_{\mathrm{in}}/V_{\mathrm{out}}\). 12 V to 24 V is 50%. \(T_{\mathrm{on}}=D/f_{\mathrm{sw}}\) is how long SW sits at 0 V while \(L\) charges from VIN.
2
The inductor carries more than the load.
Average \(I_L=I_{\mathrm{out}}/(1-D)\). 12 V to 48 V is 75% duty, so \(I_{L,\mathrm{avg}}\) jumps to 8 A at a 2 A load. The sync FET carries \(I_L\) only during the off-time, which is why output RMS is higher than \(I_{\mathrm{out}}\). Input current is the continuous inductor triangle.
3
Ripple lives on the inductor.
\(\Delta I_{L(\mathrm{pp})}=V_{\mathrm{in}}D/(L\,f_{\mathrm{sw}})\). Tight \(L\) fattens the triangle without changing duty.
4
Dead time is a diode interval.
Both FETs off: SW goes to \(-V_f\) (silicon body diode ~0.7 V) and sync-FET current is zero. This preset stretches dead time and zooms the notch on VSW.
5
Zoom the GaN edge.
At 1× you see two periods. At 20× the dead-time notch is the whole story. GaN uses this model's ~2 V \(V_{\mathrm{th}}\) instead of the silicon body diode.
6
CCM and ideal parts.
Back on 12 V to 24 V. This lab assumes continuous conduction and no closed-loop correction. If \(V_{\mathrm{out}}\le V_{\mathrm{in}}\) a boost has nothing to do.

Ideal CCM waveforms, not a loop design. The RHP zero still limits how high crossover can sit. LTspice download follows FET type (silicon LTC7063 vs GaN LT8418).

Vin (V) Vout (V) L (µH) fsw (kHz) Iout (A) Dead time (ns) FET type Zoom (edge) 1×

Synchronous boost

Low-side MOSFET grounds SW during on-time (\(L\) charges from VIN). High-side MOSFET (sync FET) ties SW to VOUT during off-time (\(L\) discharges into the load).

X: - µs, Y: - V

X: - µs, Y: - A

\( D = 1 - \frac{V_{in}}{V_{out}} = \) 0%

\( T_{on} = \frac{D}{f_{sw}} = \) 0 ns

\( T_{off} = \frac{1-D}{f_{sw}} = \) 0 ns

\( \Delta I_{L(pp)} = \frac{V_{in} \cdot D}{L \cdot f_{sw}} = \) 0 A (0% of Iavg)

Avg inductor current = 0 A

Peak = 0 A · Valley = 0 A

Output RMS = 0 A (ripple + rectified)

Try it: start on 12 → 24 V. Hit 12 → 48 V — \(D\) goes to 75% and \(I_{L,\mathrm{avg}}\) jumps to 8 A at a 2 A load. Then GaN, 1 MHz and crank zoom to see the deeper SW notch versus silicon’s 0.7 V body diode. Tight L fattens \(\Delta I_L\) without changing duty.