PLL Loop Filter Visualizer — Analog Intuition

Loop Filter Parameters

C1 (pF):

High-freq pole approx: \( f_{p1} = \frac{1}{2\pi R_1 C_1} \)

R1 (Ω):

Zero: \( f_z = \frac{1}{2\pi R_1 C_2} \)

C2 (nF):

Zero: \( f_z = \frac{1}{2\pi R_1 C_2} \)

R2 (Ω):

Damping, high-freq pole approx: \( f_{p2} = \frac{1}{2\pi R_2 C_3} \)

C3 (pF):

High-freq pole approx: \( f_{p2} = \frac{1}{2\pi R_2 C_3} \)

R3 (Ω):

High-freq pole approx: \( f_{p3} = \frac{1}{2\pi R_3 (C_4 + C_5)} \)

C4 (pF):

High-freq pole approx: \( f_{p3} = \frac{1}{2\pi R_3 (C_4 + C_5)} \)

C5 (pF): Fixed internal VTUNE capacitance, typical 54 pF

High-freq pole approx: \( f_{p3} = \frac{1}{2\pi R_3 (C_4 + C_5)} \)

I_CP (mA):

K_VCO (MHz/V):

Typical range: 50–150 MHz/V

N (division ratio):

X-Axis Min (kHz):

X-Axis Max (kHz):

Open-Loop Gain

X: - kHz, Y: - dB

Open-Loop Gain G(s): \( G(s) = \)

DC Impedance: - (Low-freq gain normalized)

Loop Bandwidth: - kHz

Phase Margin: - °

Zero (R1·C2): -

Pole 1 (R1·C1): -

Pole 2 (R2·C3): -

Pole 3 (R3·(C4+C5)): -

Understanding the PLL Loop Filter

This tool is meant to help you develop intuition for how each passive component in a typical 3rd-order charge-pump PLL loop filter contributes to the open-loop gain.

In most feedback systems, the designer focuses primarily on the crossover frequency and phase margin. These quantities strongly influence stability and settling behavior.

PLLs have an extra requirement: they must also provide good high-frequency noise rejection. The charge pump delivers current in short pulses, creating ripple at the reference frequency and its harmonics. Because the VCO is extremely sensitive to voltage fluctuations on its control input, any of this high-frequency noise that passes through the loop filter appears as spurs or phase noise on the output.

This is why a practical PLL loop filter usually contains multiple high-frequency poles in addition to the zero used for phase boost. The two high-frequency poles (created by R2·C3 and R3·(C4+C5) in the common topology) roll off the gain well above the loop bandwidth, attenuating charge-pump noise and other high-frequency disturbances.

By adjusting the component values while watching how the poles and zero move on the Bode plot, you can see the fundamental trade-off in PLL loop filter design: a wider loop bandwidth gives faster locking and better VCO noise suppression inside the loop, but it also passes more high-frequency noise. The high-frequency poles let you recover some of that rejection without destroying the desired loop dynamics.