DCM Ringing on the Scope

Part 20 · Voltage Regulation · page 2 of 3

Key point: when \(i_L\) hits zero the sync FET lets go. SW is then undriven, so \(L\) and \(C_{\mathrm{oss}}\) ring. That photo is DCM, not a second gate pulse.

12 V to 5 V. Blue band: FET off, \(i_L\) held at 0. The wiggle is on SW.

1
The FET lets go.
IOUT 0.25 A, D 25 %, 150 kHz, L 10 µH, Coss 330 pF. Δi_L/2 is 0.58 A, so 0.25 A is under it. Idle is 2.67 µs. f_ring is 2.77 MHz. i_L stays at 0 in the blue band.
2
The current probe still reads zero.
Coss 80 pF. f_ring jumps to 5.63 MHz. Idle is still 2.67 µs. I_L,min is 0.00 A. A tank current flows in Coss. On this amp scale the trace stays on zero.
3
A bigger Coss slows the same ring.
Coss 1200 pF. f_ring is 1.45 MHz. Same idle, same zero current. SW rings toward 5 V. Same event, not a layout fault and not a second pulse.
4
Raise L and the ring leaves.
L 47 µH, Coss back to 330 pF. I_L,min is 0.13 A. Δi_L/2 is 0.12 A. Mode says CCM. Idle is none. SW is VIN, then 0. The FET never releases.
5
Or raise the load past the valley.
L back to 10 µH. IOUT 0.8 A. Δi_L/2 is 0.58 A, so 0.8 A clears it. I_L,min is 0.22 A. I_L,pk is 1.38 A. No blue band. Do not let the triangle hit zero.

\(C_{\mathrm{oss}}(V)\), board capacitance, and a snubber are not drawn. The tank current is real and too small for this amp scale.

After the sync FET releases

12 V → 5 V buck · blue = FET off, iL held at 0, SW ring is normal

IOUT A D % fsw kHz L µH Coss pF

0 µs

iL · ramps, then stays at 0 after the FET releases

vSW · expected ring after release · L with Coss

D—

f_sw—

t_idle—

f_ring—

Mode—

I_L,min—

Δi_L/2—

I_L,pk—

Blue band = sync FET has released. \(i_L\) stays at 0; the wiggle is on SW. CCM: \(I_{\mathrm{OUT}}>\Delta i_L/2\), no blue band.