The Need for Regulation

Part 1 · Voltage Regulation

Key point: the load needs a voltage window. Setpoint accuracy places you inside it. How hard and how fast the load steps, against how quick the regulator is, decides whether you stay there.

Left chart is \(V_{\mathrm{OUT}}\). Right chart is \(I_{\mathrm{LOAD}}\). Green band is 3.3 V ±5%.

1
The load has a spec.
Easy load, small step, fast enough loop. The trace stays in the green band.
2
DC error eats the margin.
Vref and the feedback divider shift \(V_{\mathrm{set}}\) before the load moves. −3.5% with the easy step is still inside, with less of the window left.
3
The load step is the stimulus.
700 mA at 80 mA/µs. Same 35 µs loop. The dip and the release overshoot leave the band. Red is out of spec.
4
A faster loop catches it.
Same 700 mA edge. Response time at the fast stop of the knob, 5 µs. The dip comes back inside the window.
5
A slow loop fails a milder step.
120 µs response, 350 mA. The edge is not extreme. The loop is. That is the usual way out of the window.

Toy model, not SPICE. Peak excursion grows when the edge is large or fast and \(t_{\mathrm{resp}}\) is long. Next is the resistor divider as a soft source, then \(Z_{\mathrm{out}}(f)\).

Stay in band

3.3 V ±5% · load step and release

DC setpoint error (% · Vref + divider) Response time (µs) Load step amplitude (mA) Load slew rate (mA/µs)

\(V_{\mathrm{OUT}}\) · blue in spec · red out · green ±5%

\(I_{\mathrm{LOAD}}\) · step up, then release

Status—

Setpoint—

Peak low / high—

Edge time · peak |ΔV|—

Time out of band—

\(V_{\mathrm{set}} = V_{\mathrm{ideal}}(1+\varepsilon_{\mathrm{DC}})\)

→ —

\(t_{\mathrm{edge}} = \Delta I / \mathrm{slew}\)

→ —

\(\Delta V_{\mathrm{pk}} \propto \Delta I \cdot t_{\mathrm{resp}}/(t_{\mathrm{resp}}+t_{\mathrm{edge}})\)

→ —