Inverting Buck-Boost Waveforms

Power · inverting buck-boost

Inverting buck-boost timing & current ripple

Key point: a positive \(V_{\mathrm{in}}\) becomes a negative \(V_{\mathrm{out}}\). CCM duty is \(D=|V_{\mathrm{out}}|/(V_{\mathrm{in}}+|V_{\mathrm{out}}|)\), not \(V_{\mathrm{out}}/V_{\mathrm{in}}\). Switch node flies from \(+V_{\mathrm{in}}\) down to \(V_{\mathrm{out}}\); inductor current averages \(|I_{\mathrm{out}}|/(1-D)\).

Steps 4 and 5 keep the 12 V to −5 V rail and only change dead time and zoom.

1
Duty is not \(V_{\mathrm{out}}/V_{\mathrm{in}}\).
Inverting CCM uses \(D=|V_{\mathrm{out}}|/(V_{\mathrm{in}}+|V_{\mathrm{out}}|)\). Both rails set the on-time. 12 V to −5 V is about 29%, not 42%. Control FET on: SW sits at \(+V_{\mathrm{in}}\). Sync FET on: SW sits at negative \(V_{\mathrm{out}}\).
2
SW really does change sign.
12 V to −12 V. The node flies from +12 V to −12 V, and \(D\) hits 50%. \(I_{L,\mathrm{avg}}\) doubles for the same \(|I_{\mathrm{out}}|\).
3
Ripple uses \(V_{\mathrm{in}}\) and \(D\).
\(\Delta I_{L(\mathrm{pp})}=V_{\mathrm{in}}D/(L f_{\mathrm{sw}})\). Average inductor current is \(|I_{\mathrm{out}}|/(1-D)\), and it climbs as \(|V_{\mathrm{out}}|\) grows. 5 V to −12 V is that climb. Both ports are rectified: control FET is \(I_{\mathrm{in}}\) only during \(T_{\mathrm{on}}\), sync FET is \(|I_{\mathrm{out}}|\) only during \(T_{\mathrm{off}}\).
4
Dead time is a diode interval.
Back on 12 V to −5 V, silicon, 40 ns dead time. Both FETs off; SW parks at \(-V_f\), about −0.7 V.
5
Zoom is for the notch, not the triangle.
The \(I_L\) ramp is obvious at 1×. The same 40 ns sliver at 20× is the dead-time notch on SW.
6
GaN parks the notch at −2 V.
This lab's GaN path uses 2 V instead of the silicon body diode. Zoom stays at 20× so you can compare the clamp.

Ideal CCM, lumped \(L\), no parasitics. Closed-loop control is what actually holds \(V_{\mathrm{out}}\). This lab shows timing and current for the rails you typed.

Vin (V) Vout (V) L (µH) fsw (kHz) |Iout| (A) Dead time (ns) FET type Zoom (rising edge) 1×

Inverting topology

Control FET on: SW at \(V_{\mathrm{in}}\), inductor charges. Sync FET on: SW at negative \(V_{\mathrm{out}}\), inductor discharges into the load.

X: - µs, Y: - V

X: - µs, Y: - A

\( D = \dfrac{|V_{\mathrm{out}}|}{V_{\mathrm{in}}+|V_{\mathrm{out}}|} \) 0% \( T_{\mathrm{on}} \) 0 ns \( T_{\mathrm{off}} \) 0 ns

\( \Delta I_{L(\mathrm{pp})} = \dfrac{V_{\mathrm{in}} D}{L f_{\mathrm{sw}}} \) 0 A (0% of \(I_{L,\mathrm{avg}}\))

\( I_{L,\mathrm{avg}} = |I_{\mathrm{out}}|/(1-D) \) 0 A peak 0 A valley 0 A

Output RMS 0 A Input RMS 0 A

Try it: start on 12 V → −5 V (\(D\approx 29\%\)). Jump to 12 V → −12 V: \(D\) hits 50% and \(I_{L,\mathrm{avg}}\) doubles for the same \(|I_{\mathrm{out}}|\). Then 5 V → −12 V and watch inductor current climb. Zoom the edge and switch Silicon vs GaN — the dead-time notch sits at −0.7 V or −2 V.