Power / analog
Regulator feedback divider
Key point: the loop holds FB at \(V_{\mathrm{REF}}\), so \(V_{\mathrm{OUT}}\) is a
ratio . Standard E-series resistors snap that ratio; tolerance then opens a voltage window
you have to leave room for.
Same story as
Voltage Regulation · Part 1 .
Along the way
1
The loop sets the tap, not the rail.
\(V_{\mathrm{OUT}} = V_{\mathrm{REF}}\,(1 + R_{\mathrm{TOP}}/R_{\mathrm{BOT}})\).
Same idea as LTPowerCAD’s divider sheet — pick two catalog values, not two ideal ohms.
2
E-series residual is not zero.
Even 0.1% parts sit on a grid. The scatter is nearby legal pairs:
horizontal = setpoint error, vertical = divider current.
Hover a bubble for the ohms; leftover spec is what the load step can still use.
3
Stack the limits; do not RSS.
\(V_{\mathrm{REF}}\) and the two resistors can all sit at their datasheet ends at once,
so the gauge is those four corners — absolute worst case, a guarantee.
Root-sum-square would shrink the bar toward a typical lot; we do not use it here.
Paste datasheet \(V_{\mathrm{REF}}\) min/max in volts if the band is not a round percent.
Green is the spec you typed. Headroom is not symmetric:
transient + is room for overshoot, transient − for sag.
4
Current vs bias current.
\(I_B\) is current the FB pin sinks from the tap — it does not source.
It is not a DC you cancel with a slightly different pair; the amount moves
(part, temperature). The search ignores it and keeps the ratio.
The window then grows high by up to \(I_B R_{\mathrm{TOP}}\) (typed value as a max,
which may be zero). If that eats the spec, raise \(I_{\mathrm{DIV}}\)
(smaller resistors). Too much \(I_{\mathrm{DIV}}\) wastes quiescent power.
5
Fix one resistor when the BOM already has it.
Modes match the Excel sheet: suggest both, or lock \(R_{\mathrm{TOP}}\) / \(R_{\mathrm{BOT}}\).
6
This is the feedback string on a regulator (FB held at \(V_{\mathrm{REF}}\)).
Enable threshold
is a different job: UVLO / enable-pin ramps, leakage, and \(C_{\mathrm{filt}}\).
Reay Labs has a related
Voltage Regulator
picker and a
Resistor Finder .
Setpoint vs spec
Absolute corners, not RSS
RTOP —
RBOT —
Nominal VOUT —
Setpoint error —
Worst VOUT —
IDIV —
IB·RTOP —
Transient + —
Transient − —
\[ V_{\mathrm{OUT}} = V_{\mathrm{REF}}\Big(1+\dfrac{R_{\mathrm{TOP}}}{R_{\mathrm{BOT}}}\Big) + I_B R_{\mathrm{TOP}} \]
=
—
\[ \varepsilon = (V_{\mathrm{OUT}}-V_{\mathrm{target}})/V_{\mathrm{target}} \]
=
—
Try it: start on 3.3 V · 0.1% · in spec , then
3.3 V · 1% · leaves spec . The nominal pair still looks close; worst-case DC has
already eaten the ±2% window. Then 3.3 V · 1% · wide spec — same 1% parts,
±5% spec, back in the green. Click a scatter bubble to lock that pair.
RTOP
RBOT
VOUT
Error
IDIV