Feedback Divider — Analog Intuition

Power / analog

Regulator feedback divider

Key point: the loop holds FB at \(V_{\mathrm{REF}}\), so \(V_{\mathrm{OUT}}\) is a ratio. Standard E-series resistors snap that ratio. Tolerance then opens a voltage window you have to leave room for. Same story as Voltage Regulation · Part 1.

1
The loop sets the tap, not the rail.
\(V_{\mathrm{OUT}} = V_{\mathrm{REF}}\,(1 + R_{\mathrm{TOP}}/R_{\mathrm{BOT}})\). Same idea as LTPowerCAD's divider sheet: pick two catalog values, not two ideal ohms. 3.3 V, 0.1% parts, ±2% spec, still in the window.
2
E-series residual is not zero.
Even 0.1% parts sit on a grid. The scatter is nearby legal pairs: horizontal is setpoint error, vertical is divider current. Hover a bubble for the ohms. Leftover spec is what the load step can still use.
3
Stack the limits. Do not RSS.
\(V_{\mathrm{REF}}\) and both resistors can sit at datasheet ends at once. The gauge is those four corners, a guarantee, not a typical lot. Green is the spec you typed. 1% parts on a ±2% window: the nominal pair still looks close, and worst-case DC has already eaten the spec.
4
Current vs bias current.
\(I_B\) is current the FB pin sinks from the tap, not a DC you cancel in the ratio. The window grows high by up to \(I_B R_{\mathrm{TOP}}\). If that eats the spec, raise \(I_{\mathrm{DIV}}\) (smaller resistors). The 1% case is still on screen.
5
Fix one resistor when the BOM already has it.
Modes match the Excel sheet: suggest both, or lock \(R_{\mathrm{TOP}}\) / \(R_{\mathrm{BOT}}\). The mode control is in the lab. This step does not change the numbers.
6
Leave room for the load step.
Divider error is DC setpoint. Whatever spec remains is for transient. Same 1% parts, ±5% spec, back in the green. See need for regulation and why the divider fails.

This is the feedback string on a regulator (FB held at \(V_{\mathrm{REF}}\)). Enable threshold is a different job: UVLO / enable-pin ramps, leakage, and \(C_{\mathrm{filt}}\). Reay Labs has a related Voltage Regulator picker and a Resistor Finder.

Setpoint

VOUT (V) VREF typ (V)

VREF spec

Resistors

Series Tol (%)

Search & bias

Mode Fixed R (kΩ) IDIV (µA) IB max (nA)

Feedback string

Setpoint vs spec

Absolute corners, not RSS

Spec (±%)

RTOP—

RBOT—

Nominal VOUT—

Setpoint error—

Worst VOUT—

IDIV—

IB·RTOP—

Transient +—

Transient −—

\[ V_{\mathrm{OUT}} = V_{\mathrm{REF}}\Big(1+\dfrac{R_{\mathrm{TOP}}}{R_{\mathrm{BOT}}}\Big) + I_B R_{\mathrm{TOP}} \]

= —

\[ \varepsilon = (V_{\mathrm{OUT}}-V_{\mathrm{target}})/V_{\mathrm{target}} \]

= —

Try it: start on 3.3 V · 0.1% · in spec, then 3.3 V · 1% · leaves spec. The nominal pair still looks close; worst-case DC has already eaten the ±2% window. Then 3.3 V · 1% · wide spec — same 1% parts, ±5% spec, back in the green. Click a scatter bubble to lock that pair.

RTOP	RBOT	VOUT	Error	IDIV

Nearest standard (Ω)

Closest in selected series —